An integrated circuit, such as an application specific integrated circuit (ASIC) may include bidirectional input/output (I/O) ports that are used to both send and receive data over the same set of wires. One difficulty in implementing such bidirectional I/O ports is to ensure two separate integrated circuits do not both simultaneously try to send data over the same set of wires at circuit power-up. This can happen, for example with an IEEE 1284 connection between devices, for example, a host and a printer. Concurrent driving of the same wires by two different integrated circuits can degrade reliability of the integrated circuits, increase radio frequency interference (RFI) and/or destroy ports connected to the wires.
Therefore, at power-up, each integrated circuit is responsible to inhibit driving data over bidirectional I/O ports. ASICs in prior art solutions have utilized a reset signal to disable driving data over I/O ports during power-up. The reset signal is generated from the printed circuit board (PCB) on which the ASIC resides. The circuitry within the ASIC that processes the reset signal typically performs a synchronization before forwarding the reset signal to I/O ports. Such synchronization utilizes a system clock originating outside the ASIC. However, the system clock can be tardy in becoming functional during power-up. Until the system clock is functional, synchronization circuitry is unable to pass the reset signal to the I/O ports and the result can be a “drive fight” where two integrated circuits attempt to simultaneously drive values on the same wires. The drive fight will persist until the system clock is functional and a reset signal reaches a bidirectional I/O port for one of the integrated circuits.
One way to speed up the arrival of the reset signal at a bidirectional I/O port is to provide an asynchronous path for the reset signal to the I/O port. This is done, for example, by using the reset signal to clear the flip-flops of the synchronization circuitry in order to allow the reset signal to reach the I/O ports without the necessity of waiting for the system clock to be functional and to make the synchronization circuitry operational. The synchronization circuitry performs synchronization only when the reset is de-asserted. However, this solution can result in inadequate protection against electro-static discharge (ESD). If during normal operations, a reset input is subject to ESD, this can result in a spurious signal erroneously clearing the flip-flops of the synchronization circuitry and a resulting spurious reset signal performing a reset on part or all of the integrated circuit.